1. Field of the Invention
The present invention relates to an ATM (Asynchronous Transfer Mode) cell switching system in which information such as voices, data, and images are divided into each fixed length of cell and switched at a very high speed, and in particular relates to an ATM cell switching system capable of realizing a cell sequence control in the switching process using a simplified method.
2. Description of the Related (Prior) Art
Greatest concerns at the present time in this field are directed to the high speed cell switching system in which all the information, such as voices, data, and images, are divided into cells each of which is a fixed length of packet, the information is cellulated at a very high speed and is transmitted and switched using a simplified protocol. For such cell switching devices used in the high speed cell switching system, see the Articles, for example, Aramaki et al., "Evaluation of Delay in the Cell Distribution Type High Speed ATM Switch", in the Proceeding of the 1991 Institute of Electronics Information, and Communication Engineers. Autumn Meeting, B-305. In such Articles, there are described a cell distributing means provided corresponding to an input port, a plurality of cell switching means, and a cell sequential aligning means provided corresponding to an output port. The cell distributing means selects one cell switching means from among the plurality of cell switching means, and outputs the cell given of the time stamp showing the input time to the cell switching means. The plurality of cell switching means perform the switching processes, and the cell sequential aligning means outputs to the output port after aligning the cell output sequence using the time stamp given to the cell. The conventional cell switching system is described with its structure and operation using block diagrams in FIGS. 4, 5, and 6, assuming that two input lines are provided and a cell switching device is formed of two switch circuits.
FIG. 4 shows the cell switching device, wherein 400a, 400b depicts a cell distributing circuit, 401a, 401b depicts switch circuits receiving outputs of the cell distributing circuits 400a, 400b as inputs respectively, and 402a, 402b depicts cell sequence aligning circuits receiving outputs of the switch circuits 401a, 401b as inputs.
FIG. 5 shows the switch circuit, wherein 501 depicts a time division multiplex bus, 502a, 502b depicts address filters connected to the time division multiplex bus 501, and 503a, 503b depicts FIFO (First In First Out) buffers receiving outputs of the address filters 502a and 502b as inputs, respectively.
FIG. 6 shows the cell sequence aligning circuit, wherein 601a, 601b depict cell sequence aligning memories, and 602 depicts a time stamp minimum value detecting circuit performing outputting and inputting between the cell sequence aligning memories 601a, 601b b in respect of information.
FIGS. 4 to 6 designate examples of circuit operation. For basical circuit operation shown by the examples in FIGS. 4 and 5, the cell input from the input port is, at the cell distributing means 400a, 400b, given of the time stamp showing the input time, and is output to one switch circuit selected from a plurality of switch circuits. Thus the cell from the cell distributing means 400a, 400b is switched in accordance with address information given to the cell at the switch circuits 401a, 401b, and is output to the cell sequence aligning circuits 402a, 402b which is connected to the desired output ports. The cell sequence aligning circuits 402a, 402b output the cells to the output ports depending on the time stamp provided on the cell.
At that time, the switch circuit has a structure as shown in FIG. 5. The cell input from each input port of the switch circuit 500, is multiplexed in time division at the time division multiplex bus 501, and is input in a time divisional manner into the address filters 502a, 502b corresponding to each output port. The address filters 502a, 502b detect headers of the cells, subtract only the desirous cells, and output them to FIFO buffers 503a, 503b, which store and output the cells in a manner of "first in first out".
For operation of the cell sequence aligning circuit 600 in FIG. 6, the cells output from each switch circuit are stored in the cell sequence aligning memories 601a, 601b , provided at every switch circuit basis, which store and output the cells in a first in, first out basis. The time stamp minimum value detecting circuit 602 compares the time steps given to the cells stored in the head part of the cell sequence aligning memories 601a, 601b, to detect the smallest time-stamp, and to transmit control signals so that the cell having the smallest time-stamp is to be output from the cell sequence aligning memories 601a, 601b.
Disadvantageously, the conventional cell exchange system must compare a plurality of time stamps having a range of several bits, and further, on presence of a vacant cell sequence aligning memory, it must be confirmed that the cell having the smallest time stamp in the corresponding switch circuit does not exist. The present invention has been made for solving such problems. An object of the invention is to provide an ATM cell exchange system capable of realizing a cell sequence control by a simplified method without using a time stamp.